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Espressif Systems /ESP32-H2 /PCR /PARL_CLK_TX_CONF

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Interpret as PARL_CLK_TX_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PARL_CLK_TX_DIV_NUM0PARL_CLK_TX_SEL 0 (PARL_CLK_TX_EN)PARL_CLK_TX_EN 0 (PARL_TX_RST_EN)PARL_TX_RST_EN

Description

PARL_CLK_TX configuration register

Fields

PARL_CLK_TX_DIV_NUM

The integral part of the frequency divider factor of the parl tx clock.
PARL_CLK_TX_SEL

set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad.
PARL_CLK_TX_EN

Set 1 to enable parl tx clock
PARL_TX_RST_EN

Set 0 to reset parl tx module

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data